TR3000 RPW = 404* tPW1 - 18...

6, where tPW1 is in µs and RPW is in kilohms
15
PWIDTH
A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier ON times are controlled by the PRATE resistor as described above. It is important to keep the total capacitance between ground, Vcc and this node to less than 5 pF to maintain stability. When using the high data rate operation with the sleep mode, connect the 1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the sleep mode.
VCC2 is the positive supply voltage pin for the receiver RF section and transmitter oscillator. Pin 16 must be by-16
VCC2
passed with an RF capacitor, and isolated from the positive supply by a 100 ohm resistor. VCC2 must also be bypassed with a 10 µF tantalum capacitor. See the description of VCC1 (Pin 2) for additional information.
CNTRL1 and CNTRL0 select the receive and transmit modes. CNTRL1 and CNTRL0 both high place the unit in the receive mode. CNTRL1 high and CNTRL0 low place the unit in the ASK transmit mode. CNTRL1 low and CNTRL0 high place the unit in the OOK transmit mode. CNTRL1 and CNTRL0 both low place the unit in the 17
CNTRL1
power-down (sleep) mode. CNTRL1 is a high-impedance input (CMOS compatible). An input voltage of 0 to 200 mV is interpreted as a logic low. An input voltage of Vcc - 200 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. This pin must be held at a logic level; it cannot be left unconnected.
CNTRL0 is used with CNTRL1 to control the receive and transmit modes of the transceiver. CNTRL0 is a 18
CNTRL0
high-impedance input (CMOS compatible). An input voltage of 0 to 200 mV is interpreted as a logic low. An input voltage of Vcc - 200 mV or greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV
should not be applied to this pin. This pin must be held at a logic level; it cannot be left unconnected.
19
GND3
GND3 a transceiver RF ground pin. This pin should be connected to GND1 by a direct, low-inductance trace.
RFIO is the RF input/output pin. This pin is connected directly to the SAW filter transducer. Antennas presenting an impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series match-20
RFIO
ing coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For some impedances, two inductors and capacitor will be required. A DC path from RFIO to ground is required for ESD protection.
S M - 2 0 L C a s e D r a w i n g
A S H T r a n s c e i v e r P i n O u t
0 . 3 6 "
0 . 0 8 "
0 . 1 1 5 "
G N D 1
R F I O
( 9 . 0 2 )
( 2 . 0 3 )
( 2 . 9 2 )
1
2 0
0 . 0 2 "
( 0 . 5 1 )
V C C 1
2
1 9
G N D 3
A G C C A P
3
1 8
C N T R L 0
0 . 4 2 "
P K D E T
4
1 7
C N T R L 1
( 1 0 . 7 )
B B O U T
5
1 6
V C C 2
C M P I N
6
1 5
P W I D T H
0 . 0 4 "
( 1 . 0 2 )
R X D A T A
7
1 4
P R A T E
T X M O D
8
1 3
T H L D 1
0 . 1 3 "
( 3 . 3 0 )
L P F A D J
9
1 2
T H L D 2
1 0
1 1
G N D 2
R R E F
11
R F O u t p u t P o w e r v s I T X M
1 . 0 0 0
0 . 8 7 5
3 . 5 V
2 . 7 V
0 . 7 5 0
W 0 . 6 2 5
m
er in 0 . 5 0 0
ow
utput P 0 . 3 7 5
O
0 . 2 5 0
0 . 1 2 5
0
0 . 0 5
0 . 1 0
0 . 1 5
0 . 2 0
0 . 2 5
0 . 3 0
0 . 3 5
0 . 4 0
0 . 4 5
0 . 5 0
I
i n m A
T X M
V
v s I
T X M
T X M
1 . 0 0
0 . 9 8
0 . 9 6
0 . 9 4
V in 0 . 9 2
M
V TX
0 . 9 0
0 . 8 8
0 . 8 6
0
0 . 0 5
0 . 1 0
0 . 1 5
0 . 2 0
0 . 2 5
0 . 3 0
0 . 3 5
0 . 4 0
0 . 4 5
0 . 5 0
I
i n m A
T X M
Note: Preliminary specifications, subject to change without notice.
Revised: 1999.09.30
12